Claude Skill
Eriemon/verilog-generator
A Claude Skill for automated Verilog-2001 RTL generation workflows. Supports EDA, FPGA, and agent-based hardware design pipelines.
Overview
Stars149
Forks4
LanguagePython
Last pushed2026-05-27
Last synced2026-05-27
Repository
OwnerEriemon
Repositoryverilog-generator
Full nameEriemon/verilog-generator
Repo ID1,233,021,136
Install this Skill
git clone https://github.com/Eriemon/verilog-generator.gitRegistry
TypeUnknown
Quality scoreUnknown
VerificationUnknown
Last verifiedUnknown
Summary
A Claude Skill for automated Verilog-2001 RTL generation workflows, enabling AI-driven hardware design and FPGA development.
Chinese description
用于Verilog-2001 RTL生成工作流的Agent技能。
Key features
- Generates Verilog-2001 compliant RTL code
- Integrates with EDA and FPGA toolchains
- Supports agent-based hardware generation workflows
- Designed for codex-skill and agent-skill pipelines
Use cases
- Automated RTL generation for FPGA projects
- AI-assisted hardware design prototyping
- Streamlining Verilog coding in EDA workflows
- Rapid iteration of digital logic modules